摘要
RS码是一种纠错能力强、使用广泛的多进制循环码。首先介绍了RS编码器原理、有限域乘法器的实现方法以及设计实现的一般框图,然后以RS(204,188,8)码为例,给出了采用一般乘法器、常数乘法器和常数加法器的RS编码器的算法实现原理,并基于现场可编程门阵列FPGA给出了实现方法,根据设计实现的结果,分析了算法的优劣,最后得到了较优的设计方法。
RS code is a kind of widely used non-binary code with fine error-correcting capability. This paper describes firstly the principle of RS encoder, the implementation method of finite field multiplier and its design block diagram. Then by taking RS （204,188,8） code as an example, the paper gives the implement principle of RS encoder with common multiplier, constant multiplier and constant adder based on FPGA. The circuit for implementation and the simulation waves are also presented. Based on the design and implementation results, the paper analyzes the advantages and disadvantages of this algorithm and finally gives the superior design method.
出处
《无线电通信技术》
2009年第2期52-55,共4页
Radio Communications Technology
