摘要
为了减少互连串扰噪声对电路性能的影响,提出一种top-k延迟噪声故障分析方法。通过逻辑分析方法有效地修剪受扰线和干扰线组合的分析空间,利用时序窗口计算受扰线和干扰线之间的虚假延迟噪声故障的发生概率,找到实际电路中最有可能引起虚假延迟噪声故障的top-k条干扰线。本方法能够在规定时间内消除尽可能多的虚假噪声,从而提高了串扰噪声影响下时序分析的精确度。
To reduce the impacts of interconnection crosstalk noise on the circuit performance,this paper proposed a top-k delay noise failure analysis method.The logic relations were considered to effectively prune the analysis space of victim line and aggressor lines.Then the occurrence probability of the false delay noise failure between the victim line and aggressor line was computed using the timing window.Furthermore,the top-k aggressor lined which had the largest probabilities to cause false delay noise failures in real circuits could be found.The largest number of false failures can be filtered within runtime,producing a significant pessimism reduction for the crosstalk-aware timing analysis.
出处
《计算机应用研究》
CSCD
北大核心
2012年第1期158-160,共3页
Application Research of Computers
基金
山东省优秀中青年科学家基金资助项目(BS2009DX024
BS2010DX013)
山东省高校科技计划资助项目(J09LG34)
关键词
超大规模集成电路设计
串扰噪声
延迟噪声故障
时序分析
very large scale integration circuit design
crosstalk noise
delay noise failure
timing analysis
