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通用的层次化FPGA划分算法 被引量：2

Universal Hierarchical FPGA Partitioning Algorithm
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摘要 层次化FPGA(HFPGA)是目前工业主流的芯片架构.在前人关于HFPGA成果的基础上,提出了一种改进的划分算法.该算法将模拟退火算法与ratiocut思想结合,确定多层多划分的规模后,采用数据结构进行多分优化,在将可配置逻辑块(configurablelogicblock,CLB)划分到各个簇的时候考虑割线数的目标函数,实现了更好的划分结果,提高了FPGA芯片的利用率,优化了整个芯片的性能. HFPGA （hierarchical FPGA） partition algorithm is proposed, which based is a common FPGA architecture in industry. An improved on previous works about hierarchical FPGA partitioning. The algorithm combines the simulated annealing algorithm with ratio-cut method to ascertain the level of the multi-level multi-way partitioning. Considering the number of cut lines while partitions CLB into cluster, it achieves a better partition result and improve the usage in HFPGA, then optimize the FPGA performance.
作者 陈苑锋 唐璞山 来金梅 童家榕
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2006年第5期661-666,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(600760) 上海应用材料科技合作共同计划(0406)
关键词 层次化FPGA 划分 hierarchical FPGA partition
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献9

  • 1Wei Yen-Chuen,Cheng Chung-Kuan.Ratio cut partitioning for hierarchical designs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1991,10(7):911-920
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同被引文献21

  • 1Betz V, Rose J. Automatic generation of FPGA routing architectures from high-level descriptions [EB/OL].(2000-00-00) [2006-01-10]. http://www.eecg. toronto.edu/--vaughn/papers/fpga2000.pdf.
  • 2马晓俊．FPGA IP核设计[D]．上海：复旦大学微电子学系,2004．
  • 3Cong J, Peck J, Ding Y. RASP: A general logic synthesis system for SRAM-based FPGAs [C] //Proceedings of the 1996 ACM fourth international symposium on FPGAs. New York USA: ACM Press, 1996:137-143.
  • 4Marquardt A,Betz V,Rose J. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density [C]//Proceeding of the 1999 ACM/SIGDA seventh international symposium on FPGAs. New York,USA: ACM Press, 1999:37-46.
  • 5Betz V, Rose J. VPR:A new packing, placement and routing tool for FPGA research [C]//Proeeedings of the 7th International Workshop on Field Programmable Logic and Applications. London, UK:Oxford, 1997:1-10.
  • 6Valiente G, Martinez C. An algorithm for graph pattern-matching [C]//Proc. Fourth South American Workshop on String Processing, Volume 8 of International Informatics Series. USA: Carleton University Press, 1997: 180-197.
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  • 9Karypis G, Aggarwal R, Kumar V, et al. Multilevel hypergraph partitioning: applications in VLSI domain [J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 1999, 7(1):69-79
  • 10Kahng A B, Xu X. Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23(4):464-471

引证文献2

二级引证文献5

计算机辅助设计与图形学学报
2006年 第5期

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