摘要
数字下变频器(DDC,Digital Down Converter)是GSM-R直放站的重要组成部分,它将高速采样的数字中频信号下变频到基带,然后进行抽取,低通滤波。利用FPGA的芯片特性以及先进的软件分析和实现工具,实现了基于FPGA的数字下变频,重点研究了数字下变频器的数控振荡器NCO和多级滤波器的原理和硬件设计仿真,通过FPGA芯片Virtex-4XC4VSX35设计实现了适用于GSM-R直放站的数字下变频器,并对其进行了硬件仿真与验证,结果表明提出的方案正确可行,在工程应用中具有一定的参考价值。
DDC（Digital Down Converter） is an important part of GSM-R repeater,which lets the high-speed-sampled digital signals down-converted to base band,and then implements extraction,and low-pass filtering.A DDC module is implemented by FPGA chip and advanced software analysis and implementation tools.This paper focuses on the principle and hardware design of NCO part and FIR decimation filter part of Digital Down Converter.Digital Down Converter suitable for GSM-R repeater is implemented in FPGA chip Virtex-4 XC4VSX35.The hardware simulation and verification indicate that the proposed scheme in this paper is of great reference value in the engineering application.
出处
《通信技术》
2011年第10期83-85,87,共4页
Communications Technology
