摘要
以超长指令字(VLIW)数字信号处理器(DSP)作为平台,针对现有提高单线程取指流水线效率的方法中存在的弊端,提出了一种高性能的取指流水架构。该架构支持无效取指的检测与作废,从而降低不必要的cache访问,减少取指流水停顿周期,该结构还引入专用硬件支持编译调度的循环软流水,有效提高指令并行性,降低代码存储空间,由此释放出的单线程取指流水线的空闲周期约达46.34%。实验结果表明,相比优化前的取指流水而言,代码空间压缩约11.93%,执行周期缩短约8.67%,cache访问次数下降约12.84%,指令cache暂停周期缩短约7.86%,处理器单线程的指令吞吐率平均提高约11.7%。
For the drawbacks existent in single-thread fetch pipeline to improve the efficiency, a high-pefformance fetch pipeline structure is proposed in this paper based on the platform of the VLIW digital signal processor （DSP）. It can support the detection and void for the invalid fetch, bypass for the missing fetch, which reduces the unnecessary cache access and fetch pipeline stall. The structure also inducts dedicated hardware which supports the software pipeline of scheduled compilation to improve the parallelism of instruction. It reduces the code memory space, and the idle cycles of released single-threaded pipeline is reached up to about 46.34%. Compared with the fetch pipeline before optimized, experiment results show that the code storage space is reduced about 11.93%, the average execution cycle is shortened about 8.67%, the cache access times is decreased about 12.84%, the suspension period of instruction cache is shortened about 7.86%, and the single-threaded instruction throughput of processor is increased by 11.7%.
出处
《国防科技大学学报》
EI
CAS
CSCD
北大核心
2011年第4期102-106,共5页
Journal of National University of Defense Technology
基金
国家科技重大专门资助项目(2009ZX01034-001-006)
关键词
数字信号处理器
无效取指
软件流水
循环缓冲
digital signal processor
invalid instruction fetch
software pipeline
loop buffer
