摘要
Twofish算法是AES加密标准的最终5个候选算法之一.以SOPC技术为基础,依据算法在不同密钥长度下的相似性,设计了一个可分时复用的Twofish加/解密处理单元.该设计以优化硬件结构为目标,在不降低原Twofish算法安全性的前提下,改进了S-boxes设计,与传统的Twofish系统相比有加密速率更快和资源消耗更少等优点.本设计采用VHDL硬件描述语言设计,采用QuartusⅡ8.0进行了综合与布线,并将该处理单元封装成为独立的IP核,挂接在Altera公司提供的NiosⅡ系统内,并最终以Altera公司的EP2C20F484C6芯片为下载目标进行验证,达到了设计要求.
The Twofish algorithm is one of the final five candidate＇s algorithms for the AES encryption standard.In this paper,follow the similar of the algorithms in different key length,we designed a time-multiplexed Twofish encryption / decryption processing unit based on SOPC technology.In order to optimize the hardware structure of the target without compromising the safety of the original premise,we revised the design of S-boxes.Compared with the traditional system,it encryption speed faster and consume fewer resources,and so on.This design uses VHDL hardware description language,and layout and wire on Quartus Ⅱ8.0.And then encapsulation this processing unit into an independent IP-core,attached to the Altera Nios-Ⅱ system,and eventually downloads to Altera EP2C20F484C6 target chip for validation.
出处
《云南大学学报（自然科学版）》
CAS
CSCD
北大核心
2011年第4期397-401,405,共6页
Journal of Yunnan University(Natural Sciences Edition)
基金
云南大学2010年度研究生优秀教材建设基金资助项目
