摘要
现代先进微处理器有非常高的集成度和复杂度，又有寄存器堆、 Ｃａｃｈｅ等嵌入式部件，而且芯片管脚数相对较少，必须要有一定的自测试设计和其它的可测试性设计来简化测试代码，提高故障覆盖率。本文简要讨论了 Ｎ Ｒ Ｓ４０００ 微处理器芯片的以边界扫描测试为主体，以自测试为补充的可测试性设计框架。着重介绍了芯片的边界扫描设计和芯片中译码控制器 Ｐ Ｌ Ａ 和微程序 Ｒ Ｏ Ｍ 以及采用内嵌 Ｒ Ａ Ｍ 结构的指令 Ｃａｃｈｅ 和寄存器堆的内建自测试设计。结果表明，这些可测试性设计大大缩短了测试代码的长度。
Department of Computer Science and Engineering Northwestern Polytechnical University, Xi′an 710072The design of a 32 bit RISC microprocessor NRS4000 was completed in 1998 at Northwestern Polytechnical University. We participated in the design, which of course took into consideration testability in order to simplify test pattern generation, and to decrease test complexity. NRS4000 is compatible with Intel 80960KA. In section 1, we give a summary of the NRS4000 architecture. In section 2, we describe the design of its boundary scan circuit to meet the requirements of IEEE 1149.1 standard. In section 3, we give the BIST (built in self test) design of several programmable logic arrays (PLA) and a microcode ROM. In section 4, we give the BIST design of register file and instruction cache. There are two features in our design: (1) By sharing test logic with normal operational mode logic, we keep the area overhead for testability low. (2) Linking the BIST circuits to the boundary scan test controller offers a standardized test access at both chip level and board level.
出处
《西北工业大学学报》
EI
CAS
CSCD
北大核心
1999年第3期344-349,共6页
Journal of Northwestern Polytechnical University
