摘要
为解决步进电机运动系统中电机加速和减速过程的控制等问题,将脉冲宽度调制(PWM)和现场可编程门阵列(FPGA)IP核技术应用到设计方案中。提出了一种基于可编程片上系统(SOPC)实现步进电机加减速PWM控制器IP核的设计方法,并以此说明了该设计思想及其实现途径。通过HDL硬件描述语言编写功能逻辑、Avalon总线接口与外部I/O电路,并描述了整个设计过程。利用Altera的Cyclone开发板对其功能进行了测试验证。仿真和实验结果表明,所设计的IP核能够应用于由单脉冲信号驱动的步进电机控制系统,且运行稳定。
In order to solve the problems of controlling acceleration and deceleration process of stepper motor motion system,the technology of pulse width modulation（PWM）and field programmable gate array（FPGA） IP core was investigated.A kind of PWM controller IP core for stepper motor speed-up and speed-down based on system on programmable chip（SOPC） was proposed,and then the design thought and realization way were illustrated.HDL hardware description language was used to prepare logic functions,Avalon bus interface and external I/O circuit,and the whole design process was described.The function of the design was tested and verified by Altera＇s Cyclone board.Simulation and experiment results show that the IP core can be applied in different stepper motor control system drivered by monopulse signal and the operation is stable.
出处
《机电工程》
CAS
2011年第6期708-711,共4页
Journal of Mechanical & Electrical Engineering
基金
浙江省大学生新苗计划科技成果推广资助项目(2009R406044)
关键词
可编程片上系统
步进电机
IP核
脉宽调制
加减速
Avalon总线接口
现场可编程门阵列
system on programmoble gate away（SOPC）
stepper motor
IP core
pulse width modulation（PWM）
speed-up and speed-down
Avalon bus interface
field programmable gate array（FPGA）
