摘要
在分析DDR SDRAM基本操作特性的基础上,根据DDR的时序要求,提出了一种基于Verilog HDL语言的控制器实现方案,并且根据具体的应用环境给出了不同的读写方案,以提高时钟效率。控制器逻辑的RTL在FPGA板卡上实现,仿真在Modelsim中进行,硬件的验证利用QuartusⅡ的逻辑分析仪(SignaltapⅡ)完成,以保证存储器的读写高效性与可靠性。
By analyzing the basic operating characteristics of DDR SDRAM,and the DDR timing requirements,this article proposes a controller based on VerilogHDL language implementations and gives different reading and writing programs to improve the efficiency of the clock in different application environments.The RTL of controller logic is implemented on FPGA board,simulated in the Modelsim and hardware verification,the logic analyzer(signaltapII) is used in quartusII to ensure that the memory's reading and writing efficiency and reliability.
出处
《长江大学学报（自然科学版）》
CAS
2011年第2期90-93,282,共4页
Journal of Yangtze University(Natural Science Edition)
