摘要
为提高NIOS系统的浮点计算效率,使用Verilog语言实现了单精度浮点数加减及乘法运算的功能模块,并通过波形验证其功能,依据NIOSⅡ定制指令的制定规范,将这一功能添加到SOPC Builder中,扩展出新的基于硬件电路的浮点运算指令,使之在NIOS软件环境中得到应用。通过NIOSⅡ本身软件浮点计算和新增硬件指令进行运算结果和时间上的对比,证实硬件指令计算的优越性,为NIOS下的浮点运算提供了更有效率的选择。
To improve the efficiency of floating-point arithmetic on NIPS system, a module of using Verilog to implement singleprecision floating-point addition, subtraction and multiplication is proposed, and its function in Quartus is verified through waveform simulation. According to the custom instruction feature of NIPS ii, adding this module to SOPC Builder, expanding a new hardwarebased floating-point arithmetic instruction, which can be applied in NIPS IDE. Comparing the output and calculating time between NIPS ii software arithmetic and the new hardware floating-point instructions, the superiority of the hardware instrtiction computation is verified, and a more efficient choice is provided for NIPS in floating-point arithmetic.
出处
《现代电子技术》
2011年第10期166-168,共3页
Modern Electronics Technique
