期刊文献+

二维阵列结构的流水线可重构路由进化策略

Routing Evolutionary Strategy of Pipeline Reconfigurable Structure Based on Two Dimensional Array Logic Structure
在线阅读 下载PDF
导出
摘要 流水线可重构系统设计方法是目前动态可重构系统设计的一种重要设计方法.为进一步提高流水线可重构系统的性能,讨论并提出了一种简洁高效的流水线路由进化策略:包括基于二维阵列结构的流水线路径时延大小的评估函数、可重构单元阵列使用情况的状态矩阵函数和结合评估函数和状态矩阵的最短时延路径搜索算法.通过对算法的仿真,验证了其正确性和有效性,为下一步研究流水线可重构结构路由的硬件进化方法奠定了理论基础. The design method of pipeline reconfig-arable system is the current major way in devising a dynamically reconfigurable system. To enhance the performance of pipeline reconfigurable system, this paper presents and discusses a simple and efficient pipeline routing evolutionary strategy, involving the assessment function of the pipeline path delay size based on two dimensional array structure, the state matrix function of the using state of two dimensional array logic resources, and the shortest delay path algorithm combining assessment function and state matrix. Through computer simulation, it is known that the algorithm is correct and effective, which establishes some theoretical foundation for further research on the hardware evolutionary approach of routing of pipeline reconfigurable structure.
出处 《小型微型计算机系统》 CSCD 北大核心 2011年第4期797-800,共4页 Journal of Chinese Computer Systems
基金 国家自然科学基金项目(60676014)资助 四川省应用基础研究项目(2006J13-072)资助
关键词 流水线可重构系统结构 评估函数 状态矩阵函数 路径搜索算法 pipeline reconfigurable system swucture assessment function state matrix function path search algorithm
  • 相关文献

参考文献4

二级参考文献31

  • 1覃祥菊,朱明程,张太镒,魏忠义.FPGA动态可重构技术原理及实现方法分析[J].电子器件,2004,27(2):277-282. 被引量:44
  • 2王友仁,姚睿,朱开阳,黄三傲.仿生硬件理论与技术的研究现状与发展趋势分析[J].中国科学基金,2004,18(5):273-277. 被引量:11
  • 3Doumar A, Kaneko S, Ito H. Defect and fault tolerance FPGAs by shifting the configuration data[ A]. In:Proceedings of the 14th International Symposium on Defect and Fault Tolerance in VLSI Systents[ C]. Washington : IEEE Computer Society, 1999,377-385.
  • 4Jason A. Cheatham and John M. Emmert. A survey of fault tolerant methodologies for FPGAs [ J ]. ACM Transactions on Design Automation of Electronic Systems, 2006, 11 (2) : 501-533.
  • 5Lukas Sckanina, Evolutionary functional recovery in virtual reconfigurablc circuits[ J]. ACM Journal on Emerging Technologies in Computing Systems, 2007, 3(2) : 1-21.
  • 6Nirmal Kumar P, Anandhi S, Raja Paul Perinbam J. Evolving virtual reconfigurable circuit for a fault tolerant system[ A]. In:Proceedings of IEEE Congress on Evolutionary Computation[ C]. Piscataway, NJ: IEEE Service Center, 2007,1555-1561.
  • 7ZhangZhai, Wang You-ten , Yang Shan-shan,et al. The research of self-repairing digital circuit based on embryonic cellular array [J]. Neural Computing &Applications, 2008, 17(2) :145-151.
  • 8Richard O. Canham, Andy M. Tyrrell. A hardware artificial Immune system and embryonic array for fault tolerant systems [ J]. Genetic Programming and Evolvable Machines, 2003, 4(4) :359- 382.
  • 9Lakamraju V, Tessicr R. Tolerating operational faults in clusterbased FPGAs [ C ]. In: Proceedings of the 2000 ACM/SIGDA Eighth International Workshop on Field Programmable Gate Arrays, New York: ACM, 2000,187-194.
  • 10Emmert and Bhatia. A fault tolerant technique for FPGAs [ J ]. Journal of Electronic Testing: Theory and Applications, 2000, 16: 591-606.

共引文献47

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部