期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

非晶硅薄膜晶体管的泄漏电流模型 被引量：2

Modeling of Leakage Current in Amorphous Si Thin-Film Transistors
原文传递
导出
摘要 当对a-Si∶H TFT施加较大的漏-栅电压时,其泄漏电流主要取决于空穴在漏端耗尽区内的产生过程以及被有源层内中立陷阱捕获的过程。基于价带空穴和被陷阱所捕获空穴的一维连续性方程,推导出空穴在有源层内纵向传导的逃逸率。通过描述漏端耗尽区内空穴的产生率以及在a-Si∶H层内空穴传导的逃逸率,建立了a-Si∶H TFT的泄漏电流模型,并进行了相应验证。 Hole generation in drain depletion region and its subsequent trapping in bulk a-Si∶H layer are the two most important processes influencing leakage current at high drain-gate voltages in a-Si∶H TFT.Based on 1-D continuity equations for tunneling generated holes and trapped holes,a rate used to describe the escaping probability of holes in bulk a-Si∶H layer was proposed.By considering the hole generation rate in drain depletion region and the hole escaping rate in bulk a-Si∶H layer due to hole conduction,a leakage current model for a-Si∶H TFT was developed and verified using experimental data.
作者 刘远 姚若河 李斌
机构地区 广东工业大学材料与能源学院 华南理工大学电子与信息学院
出处 《微电子学》 CAS CSCD 北大核心 2011年第1期150-154,共5页 Microelectronics
基金 国家自然科学基金资助项目(60776020) 广东工业大学博士启动项目(405105006)
关键词 非晶硅薄膜晶体管 泄漏电流 空穴传导 逃逸率 Amorphous Si thin-film transistor Leakage current Hole conduction Escape probability
分类号 TN321 [电子电信—物理电子学]
  • 相关文献

参考文献18

  • 1刘远,姚若河,李斌.非晶硅薄膜晶体管中不饱和输出电流的数值仿真[J].华南理工大学学报（自然科学版）,2009,37(1):15-18. 被引量：5
  • 2SERVATI P, NATHAN A. Modeling of the reverse characteristics of a -Si : H TFTs [J]. IEEE Trans Elec Dev, 2002, 49(5): 812-819.
  • 3SERVATI P, NATHAN A, SAZONOV A. A physically based spice model for the leakage current in a-Si : H TlVTs accounting for its dependencies on process, geometrical, and bias conditions [C] // Materials Research Society. San Francisco, CA, USA. 2000: A2831-A2836.
  • 4LEMMI F, STREET R A. The leakage currents of amorphous silicon thin-film transistors: channel charge emission [J]. IEEE Trans Elec Dev, 2000, 47 (12) : 2399- 2403.
  • 5LEMMI F, STREET R A. The leakage currents of amorphous silicon thin-film transistors:injection currents, back channel currents and stress effects [J]. IEEE Trans Elec Dev, 2000, 47(12): 2404-2409.
  • 6SERVATI P, NATHAN A, SAZONOV A. Effect of front hole channel on leakage characteristics of a-Si : H TFTs [C]//Proc the 12th Int Conf Microelectronics. Tehran, Iran. 2000: 247-250.
  • 7WANG L J, ZHU J, LIU C L, et al. Improvement of sub-threshold current models for a-S: H thin-film transistors [J]. Sol Sta Elec, 2007, 51(5): 703-707.
  • 8SZE S M. Physics of semiconductor devices [M]. New York: Wiley-Interscience, 1981.
  • 9PARK H R, KWON D, COHEN J D. Electrode interdependence and hole capacitance in capacitance voltage characteristics of hydrogenated amorphous silicon thinfilm transistor [J]. J Appl Plays, 1998, 83(12): 8051- 8056.
  • 10PARK H R, LEE S H, LEE B T. Characterization of the hole capacitance of hydrogenated amorphous silicon metal insulator semiconductor structures[J]. J Appl Phys, 2001, 90(12):6226-6229.

二级参考文献19

  • 1Nathan A, Kumar A, Sakariya A, et al. Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic [ J ]. IEEE Journal of Solid State Circuits, 2004,39 ( 9 ) : 1477-1486.
  • 2Liu Yuan, Yao Ruo-he, Li Bin, et al. An analytical model based on surface potential for a-Si:H thin film transistors [J]. IEEE/OSA Journal of Display Technology, 2008,4 (2) :180-187.
  • 3Thompson M J, Johnson N M, Moyer M D, et al. Thin film transistors on a-Si:H [ J]. IEEE Transactions on Electron Devices, 1982,29 ( 10 ) : 1643-1 646.
  • 4Powell M J, Orton J W. Characteristics of amorphous silicon staggered electrode thin film transistors [ J ]. Applied Physics Letters, 1984,45 ( 2 ) : 171-173.
  • 5Possin G E, Castleberry D E, Poper W W, et al. Contact limited behavior in amorphous silicon FET for applications to matrix addressed liquid crystal displays [ J ]. Proceedings of the Society for Information Display, 1985,26 ( 3 ) :183-189.
  • 6Troutman R, Kotwal A. A device model for the amorphous silicon staggered electrode thin film transistor [ J ]. IEEE Transactions on Electron Devices, 1989,36 (12) : 2 915- 2 922.
  • 7Kaneko Y, Sasamo A, Tsukada T. Analysis and design of a-Si TFT/LCD panels with a pixel model [ J ]. IEEE Transactions on Electron Devices, 1989,36 ( 12 ) : 2 953- 2958.
  • 8Gadelrab S M, Chamberlain S G. The effects of metal-n^+ interface and space charge limited conduction on the performance of amorphous silicon thin film transistors [ J ]. IEEE Transactions on Electron Devices, 1994, 41(3) : 462-464.
  • 9Gadelrab S M, Chamberlain S G. An analytical model for a-Si: H transistors based on TFT device characteristics [C]//Proc of the Second International Workshop on Active Matrix Liquid Crystal Displays. Bethlehem: IEEE, 1995:29-32.
  • 10Martin S,Chiang C S, Naha J Y, et al. Influence of the amorphous silicon thickness on top gate thin film transistor electrical performances [ J ]. Japanese Journal of Applied Physics,2001,40(2) :530-537.

共引文献4

同被引文献7

引证文献2

二级引证文献2

微电子学
2011年 第1期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部