摘要
针对时钟布线提出了一种有效的变线宽算法。该算法通过对时钟树中各树枝延迟敏感度的分析，选择总体最优的连线进行变线宽处理，使得时钟树的路径延迟最小化。在延迟优化后，为了使时钟偏差小于给定的约束，通过变线宽对各时钟汇点的延迟进行合理的再分配，使延迟最大的时钟汇点延迟最小化，而延迟较小的路径延迟适当增加，以进一步改善时钟树延迟。实验结果表明，该算法有较高的运行效率，时钟树的路径延迟和时钟偏差得到了显著的改善。
An efficient wire sizing algorithm for clock network routing is presented in the paper. The sensitivity of all of the leaf nodes with respect to the selected segments is computed, then the wires with the global optimum are selected to be sized. After delay optimization, the delays of the leaf nodes are redistributed to reduce the clock skew and the delay is further reduced. Experiments indicate a significant reduction in path delay and clock skew for the proposed algorithm.
出处
《微电子学》
CAS
CSCD
北大核心
1999年第3期164-168,共5页
Microelectronics
基金
国家攻关资助
关键词
计算机辅助设计
变线宽
IC
时钟网布线
IC CAD, Wire sizing, Layout, Clock tree, Clock network routing, Clock skew
