摘要
采用IBM0.13μm CMOS工艺,设计了适用于80MS/s流水线结构A/D转换器的比较器。电路使用全差分动态锁存结构,在Lewis-Gray结构的基础上,保留比较器阈值和输入差分管尺寸之间的线性比例关系,改进复位和输出电路结构,降低了设计复杂度和功耗,减小了面积。通过细致的版图考虑,实现了7种不同阈值电压的比较器,失调小于13mV,最大面积为25μm×13μm,最高工作频率达500 MHz;80MS/s工作时,功耗最大仅为63μW,低于Lewis-Gray结构的比较器。
A low-power multi-threshold comparator for 10-bit 80 MS/s pipelined ADC was designed using IBM 0.13 μm CMOS process.The circuit,which was based on Lewis-Gray comparator prototype,retained the linear relation between threshold value of comparator and size of differential input transistors,and improved reset and output circuit structures.The proposed circuit had lower power and smaller chip size.Seven comparators with different threshold values were designed with careful layout design,which had an offset voltage less than 13 mV and a maximum operating frequency up to 500 MHz.Each comparator only occupies a chip area of 25 μm×13 μm.Operating at 80 MHz,the circuit dissipates less than 63 μW of power,which is lower than comparator based on Lewis-Grays structure.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第5期649-652,共4页
Microelectronics
基金
国家科技重大专项项目(2009ZX01034-002-002-001-02)
上海市科委项目(08706200802
08700741300
09700713800)
上海重点学科建设项目(B411)
