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DSP编译器中一种基于子图的分簇算法 被引量:1

Cluster Assign Algorithm Based on Subgraph for DSP Compiler
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摘要 为了提高发射宽度,高端DSP普遍采用分簇结构设计.分簇结构的处理器依赖编译器在代码生成的时候指定每条指令所在的簇.针对传统分簇算法中存在参考信息太过局部的问题,提出一种依据资源压力将指令依赖图划分成多个子图,然后对子图进行分簇的算法.最后,验证了该算法能够提高分簇效率. For more issue width, the clustered VLIW processor is a common design in advanced DSP. A clustered processor need compiler assign cluster to each instruction in code-generation. For the problem that traditional cluster assign algorithm using local reference information, the paper proposes an algorithm which divide dependence graph to multiple sub-graph first, then assign cluster to each sub-graph later. It is verified that the algorithm is effective .
出处 《微电子学与计算机》 CSCD 北大核心 2010年第8期49-52,56,共5页 Microelectronics & Computer
基金 核高基项目(2009ZX01034-001-001-002) 安徽省自然科学基金(090412068)
关键词 数字信号处理器 分簇 编译器 依赖图 DSP cluster compiler dependence graph
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参考文献7

  • 1胡定磊,陈书明,刘春林.分簇结构超长指令字DSP编译器的设计与实现[J].小型微型计算机系统,2006,27(2):348-353. 被引量:7
  • 2Ellis J. Bulldog: a compiler for VLIW architectures[D]. Massachusetts: CS department of MIT, 1982.
  • 3Lowney P G, Freudenberger S M. The MultiFlow trace scheduling compiler[J ]. The Journal of supexcomputing, 1995(7) :51 - 147.
  • 4Giuseppe Desoli. Instruction assignment for clustered VLIW DSP compilers: a new approach[J]. HPLab techreport, 1998(5) :32- 87.
  • 5Monica Lam. Software pipelining: an effective scheduling technique for VLIW [ C ]// proceedings of PLDI. New York, USA, ACM,1988:318- 328.
  • 6Trimaran resarch group. Trimaran manul[EB/OL]. [2010 - 01 - 10]. http://trimaran, org.
  • 7Michael L Chu. Cooperative clata and computation partitionin_g for decentralized arehiteeturesPhD - thesis [ D]. Michigan, CS department of Michigan university, 2007.

二级参考文献14

  • 1Fisher J.Very long instruction word architectures and the ELI-512[C].Proceedings of the Tenth Annual International Symposium on Computer Architecture,Stockholm,Sweden,1983,140-150.
  • 2Faraboschi P,Fisher J,Young C.Instruction scheduling for instruction level parallel processors[C].Proceedings of the IEEE,2001,89(11):1638-1659.
  • 3Kim J et al.Experience with a retargetable compiler for a commercial network processor[C].Proceedings of the 2002 International Conference on Compilers,Architecture,and Synthesis for Embedded Systems,Grenoble,France,2002,178-187.
  • 4S Rajagopalan et al.A retargetable VLIW compiler framework for DSPs with instruction level parallelism[J].IEEE Trans.on Computer-Aided Design,2001,20(11):1319-1328.
  • 5Shannon C J.The IMPACT SC140 code generator[D].MS Thesis,Department of Electrical and Computer Engineering,University of Illinois,Urbana IL,2002.
  • 6Chakrapani L N et al.Triceps:enhancing the trimaran compiler infrastructure for strongARM code generation[R].CREST Technical Report:CREST-TR-01-01.
  • 7Leupers R.Instruction scheduling for clustered VLIW DSPs[C].IEEE PACT 2000,291-300.
  • 8Lapinskii V S et al.Cluster assignment for high-performance embedded VLIW processors[J].ACM Transactions on Design Automation of Electronic Systems,2002,7(3):430-454.
  • 9Jang S et al.A code generation framework for VLIW architectures with partitioned register banks[C].In:Proceedings of the Third International Conference on Massively Parallel Computing Systems (MPCS),1998,61-69.
  • 10Chang P P et al.IMPACT:an architectural framework for multiple-instruction-issue processors[C].ISCA 1991,266-275.

共引文献6

同被引文献3

  • 1Desoli G. Instruction Assignment for Clustered VLIW DSP Compilers: A New Approach.HPL-98-13, Hewlett-Packard Laboratories,1998:1-17.
  • 2Lapinskii VS, Jacome MF, De Veciana G,Cluster assignment for high-performance embedded VLIW processors. ACM Trans. on Design Automation of Electronic Systems, 2002,7(3):430-454.
  • 3雷一鸣,洪一,徐云,姜海涛.一种基于寄存器压力的VLIWDSP分簇算法[J].计算机应用,2010,30(1):274-276. 被引量:9

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