摘要
针对一类乘同余运算,提出了一种快速算法。采用1个32位乘法、2个32位加法、少量移位操作和1个最高位分离操作方法,避免了连续减法和除法运算。采用硬件语言设计了快速算法。在此算法的基础上,设计了基于FPGA的伪随机序列发生器。
Quick algorithm for one multiplication congruence operation is put forward. A 32-bit multiplier, two 32-bit adders, a few shifters and a top-bit separation operation are needed in the algorithm, which avoids from continuous subtraction and division. The quick algorithm is designed in hardware description language. Based on the quick algorithm, the pseudo-random sequence is designed in field programmable gate array.
出处
《电子技术应用》
北大核心
2010年第7期151-153,共3页
Application of Electronic Technique
关键词
快速算法
乘同余
伪随机序列
FPGA
quick algorithm
multiplication congruence
pseudo-random sequence
FPGA
