摘要
针对雷达系统小型化和低功耗的应用需求,提出一种宽带雷达数字接收机中数字下变频器的设计方法。通过采用系统采样频率等于输入信号中心频率4倍的采样技术,结合混频器的特殊实现结构以及半带FIR滤波器抽头系数的特点,经过详细的理论推导后,给出该方法具体的硬件实现结构,能够显著降低数字下变频信号处理的复杂程度,有效减少对硬件逻辑资源,尤其是硬件乘法器的消耗。该方法在FPGA中实现时,与使用传统方法设计的数字下变频器相比,硬件逻辑资源消耗减少83.65%,功耗降低约110 mW。最后,设计实例结果验证了设计方法的正确性以及很好的工程实用性。
A designed method of DDC module in wide band radar digital receiver is proposed for the application requirements of miniaturization and low power consumption in radar system.Using the sampling technique that the system sampling frequency equaled to 4 times the intermediate frequency,combining with the special implemented structure of mixer and the tap coefficient characteristics of half-band FIR filter,the specific hardware structure was presented after detailed theoretical derivation.Signal processing complexity and hardware resource consumption of DDC are reduced significantly,especially hardware multipliers.When implementing this method in FPGA and compared with the conventional method,resources are saved by 83.65% and power consumption is reduced by about 110 mW.Finally,a design example results indicate the validity and good engineering practicability of this method.
出处
《半导体技术》
CAS
CSCD
北大核心
2010年第6期610-613,共4页
Semiconductor Technology
