摘要
针对软件无线电接收机中数字下变频的特点,提出了一种合理的基于FPGA实现宽带数字下变频的方案,即分级实现以降低抗混叠滤波器的阶数;并且每级采用不同算法实现滤波抽取以占用不同资源,从而实现FPGA总体资源的合理、高效利用。另外,论述了一种适合FIR抽取滤波器的算法——时钟选择运算法,并通过Altera公司的EP2S60F484C4对该算法进行了测试,验证了它的高效性。
Based on the discussion of the structure of digital down-conversion （DDC） in software radio receiver, this paper suggests the classification of decimation filtering to reduce the taps of the anti-aliasing filters, and the suggestion to use different resources at separate step of decimation filtering during the multiple steps, so as to make the resources of FPGA high-efficient utilization. Besides, a new algorithm - clock-selective-computing algorithm fitting for FIR decimation filter is proposed and tested by Altera＇s EP2S60F484C4. Results validate that the new algorithm spends less resources.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2008年第5期698-700,708,共4页
Journal of University of Electronic Science and Technology of China
基金
部级基金
