摘要
设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。
A sample and hold（S/H） circuit for 12 bit 40 MS/s low power pipelined A/D converters is presented.The low power was achieved by using the same OTA in S/H state and MDAC state at different time.A modified bootstrapped switch reducing nonlinearity related to input signal was designed.A gain boosted telescopic cascode amplifier was designed by optimizing the GBW of the auxiliary amplifier.The circuit was simulated and analyzed based on TSMC 0.35 μm 3.3 V CMOS process.Simulation results show that the ENOB is 11.6 bit,SFDR is 85 dB and SNDR is 72 dB.The circuit consumes 14 mW.
出处
《半导体技术》
CAS
CSCD
北大核心
2010年第5期489-494,共6页
Semiconductor Technology
基金
国家自然科学基金(60676015)
