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全差分BiCMOS采样/保持电路仿真设计

Fully-Differential Sample/Hold Circuit Using BiCMOS Technology
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摘要 在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。 A fully differential high-speed BiCMOS sample/hold（S/H） circuit is designed.The performance of the S/H circuit is decided by the high-speed and high-precision op-amp,the setting time of op-amp is only 1.37 ns.To improve the linearity of the S/H circuit,the bootstrapped switch was used,the op-amp could switch CM levels about 1.5 ns using the dual level CMFB.Based on SMIC 0.25 μm BiCMOS process,the designed S/H circuit was simulated using Cadence Spectre.The S/H circuit has a SFDR up to-61 dB,SNR up to 62 dB at a sampling rate of 250 MHz and an input frequency of 10 MHz（UP-P=1 V）,the power dissipation is only 10.85 mW.So the designed S/H circuit can be applied to low-voltage and high-speed 10 bit A/D converters.
作者 王改 成立 杨宁 吴衍 王鹏程
机构地区 江苏大学电气与信息工程学院
出处 《半导体技术》 CAS CSCD 北大核心 2010年第5期478-481,494,共5页 Semiconductor Technology
基金 国家"863"计划引导项目(2006AA10Z258)
关键词 采样/保持电路 双极互补金属氧化物半导体器件 全差分 仿真 sample/hold circuit BiCMOS devices fully differential simulation
分类号 TN432 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

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二级参考文献17

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半导体技术
2010年 第5期

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