摘要
基于预放大锁存理论,设计了一种高速钟控比较器,它包括三个主要部分:预放大器、判断级电路、输出缓冲器。在SMIC 0.18μm CMOS工艺模型和1.8 V电源电压下,采用Hspice对比较器电路进行仿真,结果表明在500 MHz的时钟频率下,精度可达0.3 mV,功耗仅为26.6μW。该电路可以应用在高速Flash ADC电路中。
Based on preamplifier-latch theory,a high-speed clocked comparator was designed.It consists of a preamplifier,a decision circuit and output buffer.Based on 0.18 μm SMIC CMOS process,the comparator circuit with a 1.8 V power supply was simulated by Hspice.The results of simulation show that it can achieve a resolution of 0.3 mV at a 500 MHz clock rate,and the power consumption is only 26.6 μW.The circuit can be used in high-speed Flash ADC design.
出处
《电子器件》
CAS
2010年第2期158-161,共4页
Chinese Journal of Electron Devices
基金
UWB多点协同定位
国家自然科学基金
TH-UWB通信专用集成电路研究
广西科学基金
关键词
钟控比较器
预放大器
正反馈
自偏置差分放大器
失调电压
clocked comparator
preamplifier
positive feedback
self-biasing differential amplifier
offset voltage
