摘要
设计了一种适用于采用级间共用运放技术的10bit流水线A/D转换器(ADC)的低功耗全差分运算跨导放大器(OTA).该放大器由一个改进的折叠共源共栅结构和一个套筒共源共栅结构共同组成,利用时钟控制,使ADC的采样保持和余量增益电路正常工作并满足其性能要求.基于0.6μmCMOS工艺对电路进行了设计,并利用HSpice软件对电路进行了仿真.仿真结果表明,该放大器在采样保持和奇数级电路中开环增益为60dB,偶数级电路开环增益为50dB,总功耗仅为4.5mW,满足低功耗ADC所要求的性能指标.
The design of a full differential,low power consumption operational transconductance amplifier（OTA） is presented,applicable to a 10-bit pipelined A/D converter（ADC） architecture in which share-OTA technology is adopted.The amplifier is cascaded with an improved folded cascode structure and a telescopic cascode structure,using the clock control to satisfy the performance requirements of the sample/hold circuit and residuegain-circuits.The circuits are designed with 0.6 μm CMOS process and simulated respectively by HSpice software.Results from the simulation show that the sample/hold and odd-class circuits have an open-loop gain of 60 dB,the even-class circuits have an open-loop gain of 50 dB,and the total power comsumption of the OTA is only 4.5 mW.All the performances of the OTA satisfy the demands of the low power A/D converter.
出处
《哈尔滨理工大学学报》
CAS
北大核心
2010年第2期83-87,共5页
Journal of Harbin University of Science and Technology
关键词
运算跨导放大器
全差分
余量增益电路
operational transconductance amplifier
full-differential
residue-gain-circuit
