摘要
介绍了一种用于∑-ΔADC的低功耗运算放大器电路。该电路采用全差分折叠-共源共栅结构,采用0.35μm CMOS工艺实现,工作于3 V电源电压。仿真结果表明,该电路的动态范围为80 dB、直流增益68 dB、单位增益带宽6.8 MHz、功耗仅为87.5μW,适用于∑-ΔADC。
A kind of low-power operation amplifier circuit for ∑-△ ADC was introduced. Fully differential folded-cascode structure was adopted and fabricated in a 0.35 μm CMOS mixed mode process with a single 3 V supply. HSPICE emulation results show that the dynamic range of the amplifier is 80 dB, openloop DC gain is 64 dB, unity-gain bandwidthis 6.8 MHZ, and the total power consumption of the device is only 87.5 μW. So it is suitable for the ∑-△ ADC.
出处
《半导体技术》
CAS
CSCD
北大核心
2007年第5期433-435,共3页
Semiconductor Technology
