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WCDMA数字中频发信机的设计 被引量:1

The Design of WCDMA Digital Intermediate Frequency Transmitter
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摘要 基于软件无线电技术的设计理念,提出了一种新型的WCDMA数字中频发信机结构:内插和滤波设计中采用根升余弦数字滤波器(RRC)、半带滤波器(HB)以及积分梳状滤波器(CIC)三者相结合的方式,在数字域进行三载合路,并使用削峰和数字预失真技术对信号进行优化处理。新型结构使得设计灵活性更大,对射频功放线性度要求更低。关键模块的Matlab仿真结果表明,三载波主要性能指标邻道泄露比(ACLR)在5 MHz和10 MHz处改善度分别为20 dB和18 dB,达到-58 dBc和-60 dBc,完全满足3GPP协议的设计要求。 This paper proposes a new structure of digital intermediate frequency transmitter based on the software defined radio:using root raised cosine filter,half-band filter and cascaded integrator Comb filter in interpolation and filter design, combine three carriers in digital domain and adopt Crest Factor Reduetion(CFR) and Digital Pro-distortion(DPD) technology to optimize the signal quality. This new structure improve the designing flexibility and lower the requirement of PA linearity. The simulation result using matlab demonstrate that:main performance index Adjacent Channel Leakage Ratio( ACPL) improve 20 dB and 18 dB at 5 MHz and 10 MHz respectively, reach to-58 dBc and-60 dBe, and meet the demands of 3GPP protocol.
出处 《宇航计测技术》 CSCD 2010年第1期43-46,共4页 Journal of Astronautic Metrology and Measurement
基金 湖南省自然科学基金项目(09JJ5041) 湖南省科技计划项目(2008FJ3123)
关键词 数字中频发信机 数字预失真 削峰 DIF Digital transmitter DPD CFR
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  • 1艾渤,张涛涛,潘长勇,杨知行,王勇,赵怀勋.高功率放大器的相位失真对系统性能的影响(英文)[J].系统仿真学报,2007,19(2):424-428. 被引量:10
  • 2.13GPP TS 25.104 V3.4.0[Z].,..
  • 3Eugene B. Hogenauer, member IEEE. An Economical Class of Digital Filters forDecimation and Interpolation, IEEE transactions on acoustics,speech and signal processing, 1981 ;asp - 29(2).
  • 4AD6634 preliminary technical data.
  • 5HyukJ. Oh, SunbinKim, Ginkyuchoi Member IEEE, and Yong H. Lee, Senior Member IEEE, On the use of Interpolated second - order polynomials for efficient filter design in programmable downconversion.
  • 6KevinSkahill.可编程逻辑系统的VHDL设计技术[M].南京:东南大学出版社,1998..
  • 7刘凌 胡永生[译].数字信号的FPGA实现[M].北京:清华大学出版社,2003..
  • 8ALTERA Data book,2001.
  • 9A.Dempster, M.Maeheod. use of Minimun_Adder Multiplier Blocks In Fir Digital Filters IEEE Transactions on Circuits and systems Ⅱ 1995.
  • 10Yun-Nan Chang, Keshab K.Parhi. High_ Performance Digital_Serial Complex Multiplier.IEEE Transactions on Circuits and systems, June 2000.

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