摘要
从时序控制的角度出发,研究提高加法器性能的方法。在研究前置进位加法器的算法和结构后,又对多米诺电路的时钟控制技术进行深入分析。结合前置进位结构和自定时时钟控制,设计了一个32 b多米诺加法器。该加法器能有效地提高时钟使用率。在TSMC 0.18μm工艺下,加法器的最大延时为970 ps,约为相同工艺下13倍FO4的延时。
From the point of time- controlling,the method of improving the performance of adder is researched. After discussing the algorithm and structure of prefix-carrying adder, the time- controlling technology of Domino circuit is analysed deeply. Combined the structure of prefix - carrying and self - timing,a 32 b Domino adder is designed. The usage of clock is enhanced efficiently by the adder. In TSMC0.18um process,the adder＇s maximal delay is 970 ps,about 13 times of the delay of FO4 in the same process.
出处
《现代电子技术》
2010年第2期19-21,共3页
Modern Electronics Technique
