摘要
与传统的流水线方法不同,最大速率流水移除了数字电路内部的同步器件,利用电路的延时特性,在一段组合电路中同时传播多个数据行波,达到了高速运算的目的。文章首先介绍了最大速率流水技术的时钟约束和使用CMOS工艺进行最大速率流水设计需要解决的问题,然后使用最大速率流水的思想设计了一个32位超前进位加法器。与传统流水的加法器的比较结果表明最大速率流水技术显著提高了加法器的运算速度。
Maximum Rate Pipeline technique removes the inner synchronous units in digital circuits, and allows multiple data waves propagating along the combinational logic at the same time, therefore leading to noticeable acceleration of computation. This paper introduced the timing constraints of Maximum Rate Pipeline and the problems of applying it onto CMOS technology, and then designed a 32-bit adder with the maximum rate pipeline requirement. Its comparison result with traditional adder reveals its noticeable superiority.
出处
《微电子学与计算机》
CSCD
北大核心
2006年第8期21-24,共4页
Microelectronics & Computer
