摘要
给出一种基于现场可编程门阵列(FPGA)的全数字实现对数模型自动增益控制器(AGC)的构架.该构架中的增益调整电路主要由平方包络检测器、基于坐标旋转数字计算(CORDIC)迭代结构的高效超越函数处理器、基于数字无限冲击响应(IIR)的环路积分器和参数可配置的控制逻辑发生器组成.包络检测器只要用阶数很低的有限冲击响应(FIR)滤波器就可以满足滤波性能.采用对称系数的转置型结构使得滤波器的乘法器个数降低一半.数字无限长冲激响应滤波器IIR逼近模拟积分器,通过简单近似处理得到一个结构和实现非常简单的数字积分器.基于CORDIC迭代的超越函数处理器可以很方便地实现对数转换器,该结构采用迭代算法可以输出任意精度的结果,并且容易实现电路资源和电路速度的折中,避免了传统算法对存储器要求高的缺点.采用全并行的流水结构使得电路最高工作时钟可达206 MHz.最后给出基于FPGA器件的设计结果和硬件仿真,实验结果和理论分析完全吻合.
An all digital architecture was presented to realize the logarithm modeled automatic gain control （AGC） loop based on field programmable gates array （FPGA） platform. The architecture is mainly made up of four modules, including envelope detector, coordinator rotation digital computer （CORDIC） based iterative realization of effective hyperbolic function, infinite impulse response （IIR） based loop filter, and reconfigurable control logic generator. Envelope detector can meet the filter performance requirement only with finite impulse response （FIR） filter of low order. Symmetric coefficient based transposed architecture reduces the number of multipliers in filter to the half. By approximation to analog integrator and suitable process, IIR based filter can simplify the architecture of digital integrator. The logarithm convertor is easy to be realized by CORDIC based iterative hyperbolic function processor. The architecture can also output with random precision, and realize the compromise of circuit resources and speed, which overcomes the high demand for random access memory （RAM） in traditional algorithms. With fully parallel pipeline architecture, the maximum working clock can achieve 206 MHz. Finally, the realization results based on the FPGA processor and the hardware simulation were given. Experimental results were consistent well with the theoretical analysis.
出处
《浙江大学学报（工学版）》
EI
CAS
CSCD
北大核心
2009年第11期1965-1969,共5页
Journal of Zhejiang University：Engineering Science
基金
通信系统信息控制技术国家重点实验室资助项目
