摘要
高速ADC(analog to digital converter,模/数转换器)对时钟质量的要求越来越高,为此介绍了一种基于时钟同步器与抖动清除器AD9516-3的低抖动时钟设计,并分析了时钟抖动对信噪比的影响,介绍了在中频数字接收机中AD9516-3的具体设计应用,引入了Signal Tap这种新的测试方法,最后测试了时钟性能,整体指标达到设计要求.
The high-speed ADC requires more and more quality of clock. The authors presented a kind of low-jitter clock AD9516-3, which is designed based on synchronization regulator and jitter eliminator. The authors also analyzed the impact of clock jitter on SNR, and presented the design and application of AD9516- 3 in IF digital receiver. A new test method of Signal Tap was introduced to test the quality of the clock. The test shows that the overall target meets the design requirements.
出处
《应用科技》
CAS
2009年第7期28-32,共5页
Applied Science and Technology
