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3.5GHz锁相环的设计 被引量：4

Design of a 3.5GHz PLL
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摘要 设计了一款整数型锁相环.从系统到具体电路对整个锁相环进行了详细的分析和仿真.电路采用SMIC 0.18μm CMOS射频工艺设计,面积为1.1mm×1.1mm,整个锁相环在1.8V电源电压下的功耗为36mW,仿真结果显示锁相环的相位噪声在-111dBc/Hz@1MHz,参考杂散为-76.4dBc. A integer-N PLL is designed. The whole PLL is analyzed and simulated in detail from system to exact circuit. The circuit is designed in SMIC 0.18/an CMOS RF process, the area is 1.1mm×1. lmm, the whole PLL consumes 36roW under a 1.8V voltage supply and the simulated result shows that the phase noise is - 111dBc/Hz@1MHz, the reference spur is - 76.4dBc.
作者 王云峰 叶青 满家汉 叶甜春
机构地区 中国科学院微电子研究所
出处 《微电子学与计算机》 CSCD 北大核心 2009年第6期43-46,共4页 Microelectronics & Computer
关键词 整数型锁相环 压控振荡器 电荷泵 integer-N phase-locked loops VCO charge-pump
分类号 TN74 [电子电信—电路与系统]
  • 相关文献

参考文献7

  • 1张涛,邹雪城,刘三清,沈绪榜.锁相环中高性能电荷泵的设计[J].微电子学与计算机,2004,21(10):169-171. 被引量：5
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二级参考文献5

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共引文献4

同被引文献22

  • 1LIN T H,TI C L,LIU Y H.Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs[J].IEEE Trans Circ Syst I,Reg Papers,2009,56(5):877-885.
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  • 7Young Wan Kim, Jae Du Yu. Phase noise model of single loop frequency synthesizer I-J]. IEEE J Sol Sta Circ, 2008, 54(1).112-119.
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引证文献4

二级引证文献8

微电子学与计算机
2009年 第6期

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