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锁相环高性能电荷泵电路的设计 被引量:1

Design of High-performance Charge-pump Circuit in PLL
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摘要 设计了一种新型电荷泵电路,该电路采用了差分反相器,可工作在2V的低电压下,具有速度快、波形平滑、结构简单、功耗低等特点.HSpice仿真结果显示,电荷泵的工作频率为10MHz时,功耗仅为0.1mW,输出信号的电压范围宽(0—2V).该电路可广泛应用于差分低功耗锁相环电路中. The paper designs a high - performance charge - pump circuit, in which the differential inverter is used, This kind of circuit can work at a low voltage of 2 V and it has the advantages of a rapid speed, a simple structure and a low power consumption. The HSpice simulation results show that the power consumption of the designed charge - pump circuit is only O, 1 m W when the working frequency is 10 MHz and the range output voltage is ahout 0 - 2 V. The circuit can be applied to PPL with the differential inverter.
机构地区 东南大学 南通大学
出处 《南通大学学报(自然科学版)》 CAS 2006年第1期74-77,共4页 Journal of Nantong University(Natural Science Edition) 
关键词 电荷泵 锁相环 CMOS charge-pump PLL CMOS
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参考文献6

  • 1[2]Chang R C,Kuo L C.A new low-voltage charge pump circuit for PLL[J].IEEE Circuits and System,2000,5 (5):701-704.
  • 2[3]Rhee W.Design of high performance CMOS charge pumps in phase locked loop[J].Proc IEEE Int Symp Circ& Syst.1999,1:545-548.
  • 3[4]Behazad Razavi.Design of Analog CMOS Intergrated Circuit[M].[S.L.]:The McGraw Hill Companies,Inc,2001.
  • 4[5]Finol J L,Durec J,Lovelace D.Building blocks for digital wireless communications in submicron technologies:an overview[C]// Second IEEE International Caracas Conference on Devices,Circuits and Systems.Margarita Island:Venezuela,1998:314-320.
  • 5[6]Hernandez E J,Diaz S A.Positive feedback CMOS chargepump circuits for PLL applications[J].IEEE Circuits and Systems,2001,2(8):836-839.
  • 6张涛,邹雪城,刘三清,沈绪榜.锁相环中高性能电荷泵的设计[J].微电子学与计算机,2004,21(10):169-171. 被引量:5

二级参考文献5

  • 1Ian A Young. A PLL clock generator with 5 to 110MHz of lock range for microprocessors[J]. IEEE J. Solid-State Circuits. 1992,27(11):1599-1607.
  • 2Van Paemel M. Analysis of a charge pump PLL: a new model[J]. IEEE Trans. on coummunications. 1994, 42(7):2490-2498.
  • 3Rhee W. Design of high performance CMOS charge pumps in phase locked loop [A].Proc IEEE Iht Symp Circ&Syst.1999, 1:545-548.
  • 4Behzad Razavi. Design of analog CMOS integrated circuits[M]. The Mc-Graw Hill Companies. 2001.
  • 5B J Sheu and C Ht. Switch-induced error voltage on a switched capacitor[J]. IEEE J. Solid-State Circuits. 1984, 19(8):519-525.

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