摘要
在分析了IEEE802.15.4关于无线传感器网络协议带有冲突避免的载波监听多点接入机制的基础上,通过采用独立的指令集、使用软件来控制射频接入流程的实现方式和复用伪随机数产生电路和CRC校验电路等技术,实现了节点芯片的CSMA/CA协处理器。给出采用了这种CSMA/CA协处理器结构的无线传感器网络节点基带芯片的FPGA硬件资源消耗情况,并搭建了该节点芯片与CC2420进行相互通信的测试平台,给出了测试结果,分析时延情况表明,节点芯片在资源有限的情况下获得了较高的处理速度,并实现了对多射频收发芯片支持的灵活性。
Hardware/Software co-design of computationally intensive systems is the preferred solution to achieve the required speed for resource-limited embedded applications. Based on the analysis of IEEE802.15.4 protocol of CSMA/CA algorithm for channels＇ competitive access, this paper presents a CSMA/CA coprocessor which is designed to work with an 8-bit microcontroller. By using independent instruction sets, software controls the RF access flow. Pseudo-random number generator circuit and CRC circuit are reused. The FPGA hardware resource consumption of the wireless sensor network node MAC circuits including CSMA/CA coprocessor is given. Finally, the test platform to communicate with the CC2420 platform is presented, and test results shows that a relatively high processing speed is achieved and multi-RF transceivers can be support flexibly.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2009年第1期132-137,共6页
Research & Progress of SSE
基金
国家863项目(No.2006AA01Z226)
