摘要
AMBA总线结构广泛应用于片上系统设计中。其中,AHB总线用于系统高性能、高时钟速率模块间通信,AHB总线接口设计分为主控模块接口设计和从模块接口设计。IDE硬盘作为高性价比的存储介质,广泛应用于海量视频数据的高带宽存取。本文鉴于AHB总线结构下对海量数据存储介质的需求,提出了本设计;阐述了AHB总线和IDE总线数据传输规范,并给出一个IDE硬盘控制器与AHB总线接口的具体实现。该设计采用Verilog HDL进行RTL级实现,用Quartus Ⅱ 6.0进行综合,并且在FPGA系统中得到了验证。
The AMBA architecture is widely used in SOC design. The AMBA AHB is used for high-performance, high- lock-frequency system modules. The AHB bus interface design consists of the AHB master and the AHB slave. IDE HD, as an acceptable memorizer, can meet the needs of great capacity and high bandwidth storage. This paper describes the AHB specification and the IDE specification briefly. Then,an implementation of the AHB interface to the IDE controller is presented. The RTL level of this design is implemented in Verilog HDL, synthesized in Quartus II 6. 0 and verified in FPGA. The paper mainly tells us a recommended technique to implement the AHB bus and the ATA interface by FPGA.
出处
《计算机工程与科学》
CSCD
北大核心
2009年第2期108-111,共4页
Computer Engineering & Science
