摘要
提出在FPGA内设计运算模块的FFT硬件加速方法。该方法采用FPGA计算字节倒置与蝶形单元,单片机只需将参数输出到相应地址,并从该地址读取结果即可完成复杂运算,起到了硬件加速的作用。实验表明,其计算速度可提高10倍。
A hardware acceleration FFT algorithm which design operation module in FPGA was proposed. This method calculates bit reversal and butterfly operation in FPGA, and complex operation results can he gotten when MCU put parameters into proper address and get results from the same address. It realizes hardware acceleration. Experiment result shows this algorithm enhances the computing speed 10 times.
出处
《航空计算技术》
2008年第5期127-130,共4页
Aeronautical Computing Technique
