摘要
利用Altera的QuartusⅡ软件开发平台在FPGA上实现了快速浮点除法器IP核的设计。该IP核的算法采用存储运算过程中的一些乘积项,有效地减少了除法运算过程中的移位操作,提高了浮点除法的运算速度及算法的效率。同时,基于FPGA的浮点除法器IP核具有很好的可移植性和复用性,适合应用到各种嵌入式和通用处理器中,从而提高复杂数字系统的设计效率,具有广泛的推广应用价值。
A rapid floating-point division IP core is designed and realized in the Altera Quartus II software development platform.With stored temporary product,it can reduce the number of shifting in the process of division,and speed up the division.Transplantation and reuse of the IP core make it be used in embedded or general purpose processor,which can improve the design efficiency of complicated digital system.It is worth to be widely propagated and applied.
出处
《河南科技大学学报（自然科学版）》
CAS
2008年第6期34-37,共4页
Journal of Henan University of Science And Technology:Natural Science
基金
河南省教育厅自然科学基金项目(200610464031)
