摘要
给出了一种新型的SRT除法器的实现,对其实现的构架和相应算法的实现过程进行了全面的描述。这种新的除法器算法在保持精度的条件下使用较小的资源;可以实现8位、16位、32位等更高位的除法运算,提高运算速度,较其它算法有更快和位数可调的优点。
The realization of a new kind of SRT divider is provided, and a complete description of its realization＇s framework and realization course of corresponding algorithm are given. This new divider＇s algorithm takes less resource while maintaining traditional precision, and it can realize more high-order division operation such as 8, 16, 32, improve the operation speed. Compared with other algorithm, it has the benefits of being speedy and digital modulation.
出处
《计算机工程与设计》
CSCD
北大核心
2007年第1期248-248,F0003,共2页
Computer Engineering and Design
关键词
除法器
算法
集成电路设计
商位
divider
algorithm
integrated circuit design
quotient bit
