摘要
本文提出一个适应调试功能的ＶＨＤＬ模型及ＶＨＤＬ模拟算法──ＶＳＩＭ．它与可视化ＶＨＤＬ原理图输入工具ＶＤＥＳ和高级图形调试器ＶＤＢＸ结合在一起，为设计者检查、修改自己的设计提供了极大的便利．该模拟器采用层次式结构行为混合模型，保存ＶＨＤＬ描述的所有信息和结构，以利于实现调试功能．模拟算法采用基于进程的事件驱动算法及层次式模块调用算法，并提供模拟时间、语句行、模块（包括元件、进程和子程序）、信号／变量、条件等各种中断类型并能继续模拟．
A hierarchical structural VHDL simulator-VSIM, which is suitable for debugging, is presented in this paper. With the visual VHDL entry tools and the high-level graphical debugger, it provides great convenience for designers to describe, understand, check and modify their designs. By applying hierarchical structural model similar to tree type, the simulation model retains all the information and structures so as to realize the debugging function. Every module in the model is shared from different paths. Therefore it can save the memory space and improve the efficiency. Based on the event-driven algorithm and the hierarchical module reference algorithm, the simulation algorithm can essentially support the whole set of VHDL and permit various interrupt types such as simulation time, line, module (including component, process and subprogram), signal and variable, condition etc. It also demonstrates the capability of continuing simulation after the interrupt.
出处
《计算机学报》
EI
CSCD
北大核心
1997年第11期996-1002,共7页
Chinese Journal of Computers
关键词
硬件描述语言
VHDL语言
VHDL模拟
算法
Hardware description language, VHDL, integrated design environment, VHDL simulation, visual debugging.
