摘要
VHDL设计是行为级的设计。利用VHDL设计电路是目前对于较复杂的电路系统进行设计时的最好选择.但设计中如何进行电路的简化直接关系到电路的复杂度及可靠性。VHDL语言的优化设计旨在充分利用CPLD/FPGA所提供的硬件资源,使项目设计能适配到一定规模的CPLD/FPGA芯片中,并提高系统的工作速度、降低系统功耗。优化的主要目标是减少适配所需要的宏单元数。本文分析了VHDL设计中容易引起电路复杂化的原因,提出了相应的解决方法。
The VHDL design is the behavior level design. Make use of VHDL design circuit is a best choice toward complex circuit system design at present. But how simplify circuit directly relation that its complication and reliability in circuit design. The optimization design of VHDL is for the purpose of making full use of hardware resources providedby CPLD/FPGA, making the item design suit to certain scale of CPLD/FPGA chip, increasing the system speed and lowering the power-waste. The intention of optimization is to reduce adapted macroceU numbers, This paper analysis to give rise to circuit complication reason in design of VHDL and expound solve method.
出处
《电子测试》
2008年第9期75-77,86,共4页
Electronic Test
