摘要
针对MIPSCPU流水线工作过程产生的数据相关,本文基于FPGA设计并实现了一种能有效解决数据相关的硬布线控制器。基于旁路方法,在控制器中对译码段、执行段和访存段进行有效的检测,并将检测信号合成为旁路控制信号,然后由旁路模块实现数据前推功能;使用VHDL实现控制器的设计;在FPGA平台上对控制器进行仿真验证,并给出CPU测试程序的仿真结果。结果表明:所设计的控制器能有效协调流水段工作,解决由数据相关产生的断流问题。
Aim at the data hazard which happens in the MIPS CPU pipeline, a based on FPGA hardwired controller was designed and implemented, and the controller can resolve data hazard. According to the bypass method, in the controller, Effective detection was carried on ID and EX and MEM stage. Then signal of detection was combined to bypass signal, at last bypass module finished forward function, The design of controller was implemented with VHDL. The validity of the controller was verified at FPGA hardware terrace, and the simulation result of test program for CPU was presented. The simulation shows that the controller makes each stage work normally and resolves the break because of data hazard.
出处
《微计算机信息》
北大核心
2008年第20期233-235,共3页
Control & Automation
