摘要
使用查找表作为滤波器的硬件实现算法,采用硬件描述语言(VHDL)和层次化、模块化的设计方法,对整个数字滤波器进行多层次功能模块的划分,完成了各个层次模块的设计,并将所有模块进行组合,设计了并行和串行有限长脉冲响应(FIR)数字滤波器。使用MAX+PLUS II软件进行各层次功能模块的设计输入、设计处理和校验,用波形编辑器绘制了仿真的时序波形图。将事先编写好的VHDL程序编译后,下载到目标器件上。整个设计过程在计算机上调试,灵活方便,设计周期很短。
It is used LUT as the hardware realized algorithm and is adopted hardware description language （VHDL） and hierarchical, modular design methods to plot entire multi-level functional module and complete all levels of the module design and combine all modules to the whole filter system. It designs FIR filter in parallel and series base on the CPLD. Using MAX ＋ PLUS Ⅱ software to design, include inputting and processing and checkout for the every administrative levels functional module. It is used waveform editor to draw out the simulation waveform. Let the compiled ~HDL program download to the object device. The whole design process is done on the computer, it is facile and fexible, and it reduces the design cycle.
出处
《微计算机信息》
北大核心
2008年第20期227-228,212,共3页
Control & Automation
