摘要
目前的ASIC设计中,时钟偏移成为限制系统时钟频率的主要因素,时钟树综合技术通过在时钟网络中插入缓冲器来减小时钟偏移。但是,有时这样做并不能达到系统要求的时钟偏移。以一款SMIC0.18μm工艺的DVBT数字电视解调芯片为例,分析了时钟偏移的产生原因。介绍了使用Synopsys公司Astro工具进行时钟树综合的方法,重点分析了在时钟树综合之前如何设置约束手动优化电路从而改善设计的时序,最后的流片结果证明该方法是有效的。
Clock skew becomes the primary factor of restricting clock frequency in current ASIC design. clock tree synthesis can reduce skew by inserting buffers, but sometimes it can＇t create a satisfactory clock network. The generation principle of clock skew was analyzed taking a SMIC 0.18 μm digital TV demodulation chip as an example. The perform of CTS （clock tree synthesis） using Synopsys Astro was analyzed, how to manually optimize the circuit in order to improve timing was focused, the validity of the method is proved by the tapeout result.
出处
《半导体技术》
CAS
CSCD
北大核心
2008年第6期527-529,共3页
Semiconductor Technology
