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基于Nios Ⅱ的EEPROM Controller Core的设计 被引量:3

Design of EEPROM Controller Core Based on Nios Ⅱ
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摘要 介绍了基于NiosⅡ的Controller Core的基本组成结构,并详细介绍了如何在SOPC中设计EEPROMController Core,用VerilogHDL语言实现其硬件逻辑部分,并编写了相关驱动程序和应用层软件,构建了基于NiosⅡ的SOPC。同时以AT24C02 EEPROM为例,通过设计的EEPROMController在Altera Stratix1S10系列的FPGA上实现了读写操作,试验结果正确。 The basic structural composition of the Controller Core based on Nios Ⅱ is introduced, and the method of designing EEPROM Controller Core in SOPC is described in detail. The hardware part was implemented by using Verilog HDL and the related drivers as well as application software were written to build the SOPC based on Nios Ⅱ. With AT24C02 EEPROM as example, through the design of EEPROM Controller, it is implemented to read and write on Stratix1S10 FPGA from Altera Corporation. The test results turn out to be correct.
作者 麦胤 柳沁
出处 《自动化仪表》 CAS 2008年第1期57-59,65,共4页 Process Automation Instrumentation
关键词 片上可编程系统 控制器 硬件描述语言 I^2C接口 驱动 SOPC Controller HDL 12C interface Drive
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  • 1Altera Corporation.Avalon bus specification reference manual [EB/OL].2003.http:∥www.altera.com/literature/lit-nio.html.
  • 2Rowson J,Sangiovanni-Vincentelli A.Interface-based design.[C].Proceedings of the 34th Annual Conference on Design Automation Conference,1997.178-183.
  • 3Altera Corporation.SOPC builder PTF file reference manual [EB/OL].2002.http:∥www.altera.com/literature/lit-nio.html.

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