摘要
多片ADC芯片并行时间交替采样能有效地提高系统的采样速率。但由于多种因素的影响,多个ADC通道间存在失配误差,严重降低了采集系统的性能。文章提出了一种多片ADC拼接系统的实现方法,该方法采用NiosⅡ软核计算出多个ADC通道间的误差,并在FPGA后端校正输出高速、高精度的数字信号。
The sample - rate can be increased effectively by individual slow ADCs. However, due to certain reasons, channel mismatches will happen in this system, which will increasingly degrade the performance of the whole ADC system. This thesis presents a realization method of mosaic system of multi - chip ADC. In this realization, Nios Ⅱ is used to calculate the errors between multi - chip ADC channels, and digital signals with high speed and high precision are outputted through FPGA correcting.
出处
《实验科学与技术》
2007年第6期20-22,144,共4页
Experiment Science and Technology
