摘要
时序验证是SoC片上系统设计中的关键问题。本文在嵌入MIPS内核的HDTV解码SoC芯片设计过程中,采用MIPS的VMC仿真模型对SoC系统进行了基于门级网表文件的软硬件协同的动态时序仿真。在仿真环境下,通过加载MIPS的Boot Loader程序对芯片的功能和时序进行有效的验证。在此基础上,用门级仿真过程中生成的VCD(Value Change Dump)文件对完成物理设计的SoC芯片的功耗进行了有效的估计和分析。
Timing verification is the key step in the SoC design flowo In the design of the HDTV SoC chip embedded with the MIPS core, we make the software and hardware co-simulation with the VMC model of MIPS, on the base of SoC gate-level netlist. In the process of verification ,the VMC load the boot loader program, which can verify the function and timing of the SoC chip effectively. In the process of the simulation, a VCD （value change dump） file can be obtained to help to estimate and analysis the power.
出处
《电子技术应用》
北大核心
2008年第1期40-43,共4页
Application of Electronic Technique
