摘要
为提高处理能力,设计了2×2并行流水结构的FPGA矩阵并作为处理核心用于高速数据采集与控制。在分析了多片FPGA的同步驱动原理以及协作模型的基础上,综合利用双时钟沿触发传输、资源重复与时间重叠技术提出了FPGA之间以及FPGA与外围A/D和D/A芯片的数据传输方案。最后揭示了光纤通信驱动的数据采集与控制过程及总线冲突解决策略。所设计的系统具有成本低、灵活性强的特点,实验表明该系统能够满足可靠性和实时性要求。
To improve processing ability, a 2 × 2 parallel-pipeline structured FPGA matrix was designed and used as a processing core for high-speed data acquisition and control. On the basis of analyzing the synchronous drive principle and cooperation model of multiple FPGAs, solutions for data transmission among FPGA chips and between FPGA and peripheral A/D or D/A chips are put forward by synthetically utilizing the technologies like dual clock edge triggered transfer, resource replication and time interleaving. The process of data acquisition and control driven by optical fiber communication and a strategy for solving data bus interference are disclosed at last. The designed system features low cost and great flexibility. The experimental result shows that the system is capable of meeting the requirements of both reliability and real-time performance.
出处
《电子测量与仪器学报》
CSCD
2007年第6期49-53,共5页
Journal of Electronic Measurement and Instrumentation
基金
国家"十五""863"计划重大专项<100nm步进扫描投影光刻机>基金资助
关键词
多FPGA
并行处理
同步控制
光纤通信
FIFO深度
multiple FPGAs, parallel processing, synchronous control, optical fiber communication, FIFO depth.
