摘要
随着高速数据传输发展的需求,在高速IC之间的时钟路径变得越来越关键,成为影响系统性能、功耗及噪声的关键因素。PECL(正电压射极耦合逻辑)信号作为一种适合高速逻辑互联的电平标准,越来越多地应用在高速A/D转换器的时钟设计中。介绍了一种交流耦合形式的PECL高速时钟设计方法。在时钟的端接设计中,采用串联终端匹配和并联终端匹配改善信号完整性,并利用HyperLynx软件进行仿真,取得了良好的效果,对于实际电路设计有良好的指导作用。
As the demand for high-speed data transmission grows, the clock path between high-speed ICs becomes critical in achieving high performance, low power, and good noise immunity. PECL signal makes this logic suitable for high-speed ADC clock design. This paper introduces the design method of AC-coupling PECL high-speed clock. The series termination and parallel termination are applied in the design of termination schemes in order to improve signal integrity. By using HyperLynx simulation software, it achieves the good performance, and makes practical circuit design more easy.
出处
《电子工程师》
2007年第12期18-21,共4页
Electronic Engineer
