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制备Cu互连悬空结构的新型工艺研究 被引量:2

Study of a Novel Freestanding Cu Interconnect Process
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摘要 为了降低集成电路中的互连延迟,采取了一种新型的集成电路Cu互连工艺,以掩膜电镀的方法制备Cu互连的叠层结构,借鉴MEMS工艺的牺牲层技术,用浓磷酸对Al2O3牺牲层进行湿法刻蚀,不仅在互连金属间介质层而且在层内介质层都形成了以空气为介质的Cu互连悬空结构。用一种叉指测试结构对以空气和聚酰亚胺为介质的互连性能进行了比较,结果表明,采用空气介质减小了互连线耦合电容,为进一步降低集成电路的互连延迟提供了途径。 A novel air-gap copper interconnects process was studied. Freestanding copper beams were prepared after removing Al2O3 sacrificial layer by wet-etching. In this copper freestanding structure, intralevel dielectric (ILD) and inter-metal dielectric (IMD) were both air-dielectric. A fork test structure was used to evaluate the air-dielectric in comparison with polyimide-dielectric interconnects. The results show that the coupling capacitance of air-dielectric interconnects is shrank greatly. In conclusion, this new process provides an opportunity for reduction of the delay due to conductor lines.
出处 《半导体技术》 CAS CSCD 北大核心 2007年第9期768-770,775,共4页 Semiconductor Technology
基金 上海市纳米专项(0552nm043) 上海市AM基金(0511)
关键词 CU互连 空气气隙 牺牲层材料 低介电常数 电容 copper interconnects air gap sacrificial layer material low dielectric constant capacitance
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参考文献8

  • 1王阳元,康晋锋.超深亚微米集成电路中的互连问题——低k介质与Cu的互连集成技术[J].Journal of Semiconductors,2002,23(11):1121-1134. 被引量:44
  • 2International technology roadmap for semiconductors (ITRS)[R].USA:the ITRS Organization,2001.
  • 3NOGUCHI J,SATO K,KONISHI N,et al.Process and reliability of air-gap Cu interconnect using 90 nm node technology[J].IEEE Transactions on Electron Devices,2005,52 (3):352-359.
  • 4UNO S,NOGUCHI J,ASHIHARA H,et al.Dual damascene process for air-gap Cu interconnect using conventional CVD films as sacrificial layers[C]//Proceedings of the IEEE 2005International Interconnect Technology Conference (IITC2005).Burlingame,USA,2005:174-176.
  • 5SUKHAREV V,SHIEH B P,CHOUDHURY R,et al.Reliability studies on multilevel interconnection with intermetal dielectric air gaps[J].Microelectronics Reliability,2001,41 (9-10):1631-1635.
  • 6GOSSET L G,FARCY A,DE PONTCHARRA J,et al.Advanced Cu interconnects using air gaps[J].Microelectronic Engineering,2005,82(3-4):321-332.
  • 7AMAL V,TORRES J,GAYET P,et al.Integration of a 3 level Cu-SiO2 air gap interconnect for sub 0.1 micron CMOS technologies[C]//International Interconnect Technology Conference.Burlingame,USA,2001:298-300.
  • 8WONG S C,LEE G Y,MA D J,et al.Modeling of interconnect capacitance,delay,and crosstalk in VLSI[J].IEEE Transactions on Semiconductor Manufacturing,2000,13 (1):108-111.

二级参考文献5

  • 1Yu Y,et al.Dielectric property and microstructure of a porous polymer material with ultralow dielectric constant[].Applied Physics Letters.1999
  • 2Plant D V,Kirk A G.Optical interconnects at the chip and board level : challenges and solutions[].Proceedings of Tricomm.2000
  • 3Davis J A,Venkatesan R,Kaloyeros A,et al.Interconnect limits on gigascale integration (GSI ) in the 21st century[].Proceedings of Tricomm.2001
  • 4Wu Z C,et al.Electrical reliability issues of integrating thin Ta and TaN barriers with Cu and low-k dielectric[].Journal of the Electrochemical Society.1999
  • 5Chang M F,Roychowdhury V P,Zhang L,et al.RF wireless interconnect for inter-and intra-chip communications[].Proceedings of Tricomm.2001

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