摘要
本文介绍了一种能降低高分辨率闪烁模／数转换器（ADC）电路复杂性的一种设计．这种高速、高分辨率ADC采用低分辨率的标准闪烁ADC板块组成，只需串联K个n位的标准闪烁ADC模块就可以构成一个k·n位高速ADC．使用本文提出的方法，可以很容易地用低分辨率的标准闪烁ADC模块实现4位和32位高速ADC．
A design for a high speed and high resolution ADC with reduced circuit complexity is proposed in this paper.This ADC is made up of some low resolution standard flash ADC modules. A k·n bit high speed ADC is developed by just cascading k number of n-bit standard flash ADC modules.Making use of the propoed design approach, high speed ADC of 24-bit and 32-bit could easily implemented with the low resolution standard flash modules.
出处
《微机发展》
1997年第3期45-47,共3页
Microcomputer Development
