摘要
Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied. Its structure is analyzed and the main parameters are proposed. A monolithic LC-tuned voltage controlled oscillator （LCVCO） with low phase noise is fabricated with TSMC 0.18μm RF （radio frequency） CMOS technology. The measured phase noise is - ll7dBc/Hz at 4MHz off the center frequency of 4. 189GHz. A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process. The measured results show that the IC can work well under a 1.8V power supply. Its total power dissipation is only 13mW.
对无线局域网接收机用锁相环型频率综合器的几项关键技术进行了研究.首先分析了锁相环型频率综合器的结构并提出了系统的主要参数.采用TSMC0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.其在4.189GHz频点上4MHz频偏处所测得的相位噪声为-117dBc/Hz.采用TSMC0.18μm混合信号CMOS工艺实现了具有低功耗的下变频模块电路.该电路在1.8V电源供电下可正常工作,功耗为13mW.
