摘要
本文在研究各种比较器失调消除技术基础上,提出了一种用于ADC电路的高速高精度比较器失调消除技术。该比较器由主动复位和共模箝位的预放大器和输出锁存器构成,通过负反馈自适应调整比较器输入失调电压,降低了开关电容沟道电荷注入和时钟馈通对比较器精度的影响。仿真结果表明,在Chartered 0.35μm COMS工艺下,电源电压3.3V,调整后的比较器失调误差为34μV,比较速率100MHz。
In this paper, all kinds of comparator offset-canceling technique are reviewed firstly, and then a new offset canceling technique for high-speed high-resolution comparator used in A/D converters is described. The comparator includes three preamplifiers, the outputting latch and offset canceling circuits. The experimental results show that after offset adjusting of the comparator, it achieves offset error about 34uV at 100MHz comparison rate under condition of a single ＋3.3 supply and a Chartered 0.35um CMOS process.
出处
《电路与系统学报》
CSCD
北大核心
2007年第1期51-54,共4页
Journal of Circuits and Systems
基金
数字电视调谐器专用芯片及产品产业化专项项目资助
国家自然科学基金资助项目(60176018)
