摘要
提出一种基于可编程逻辑阵列(FPGA)实现三相锁相环(PLL)控制器的全数字化方案。在单片FPGA中,采用硬件描述语言VerilogHDL实现了包括d,q坐标变换、PI调节器、压控振荡器(VCO)模块及其它实验用模块的三相锁相环控制算法。基于Simulink的仿真结果显示,在三相电压频率突变时,三相锁相环对输入信号频率和相位锁定时间小于两个基波周期的,稳态误差小。基于FPGA硬件逻辑实现的三相锁相环控制器实验结果表明,在三相电压畸变的输入下,动态和静态特性良好,对非线性负载和测量引起的谐波、直流偏移等干扰也不敏感,这种控制器能够满足柔性速度系统(FACTS)装置对电压和相位信息实时性和准确性的要求。
A fully digitized hardware design scheme of three phase phase-locked loop controller base on a field programmable gate arrays （FPGA） is presented.This scheme integrated d,q transformation,Pl controller,VCO module and other test modules which were all written in Verilog HDL.Simulation results based on Simulink indicate the three-phase PLL controller can lock the phase and frequency within two basic periods.Experimental results verify this controller base on FPGA can provides satisfied dynamic and static performances under aberrant three phase voltage inputs and has min sensi-tive with harmonics and unbalanced voltage caused by the nonlinear load conditions and measurement errors.The controller can satisfy the Flexible AC Transmission System （FACTS） equipments with realtime and accuracy requirements.
出处
《电力电子技术》
CSCD
北大核心
2005年第6期126-128,共3页
Power Electronics
